Field of the Disclosure
The present disclosure relates generally to processing systems and, more particularly, to a memory physical layer interface in a processing system.
Description of the Related Art
Processing systems such as systems-on-a-chip (SOCs) use memory to store data or instructions for later use. For example, an SOC may include processing units such as central processing units (CPUs), graphics processing units (GPUs), and accelerated processing units (APUs) that can read instructions or data from memory, perform operations using the instructions or data, and then write the results back into the memory. Processing systems may include a memory physical layer interface for controlling access to a memory module such as dynamic random access memory (DRAM) that can be used to store information so that the stored information can be accessed by the processing units during operation of the processing system. The memory physical layer interface in a processing system is conventionally referred to as a “memory PHY.” A memory controller is typically used to control operation of the memory PHY.
The memory PHY typically is trained using sequences exchanged over an interface between the memory PHY and the DRAM before data can be accurately read from the DRAM or written to the DRAM. A training sequence may include multiple commands such as read commands, write commands, activate commands, or other commands that are used to perform other operations. The memory PHY or the DRAM may require commands in the training sequence to be separated by a specified delay time interval. For example, when a write command is followed by a read command, the DRAM may require a delay of 8 cycles between the write command and the read command. The delay time interval may be different for different types of commands. For example, the delay time interval between two write commands may be different than the delay time interval between a write command and a read command. The delay time interval may also be different for different types of DRAM and may change as new DRAM designs or timing standards are introduced.